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Publications

Books

  • Robert Rogenmoser, "The Design of High-Speed Dynamic CMOS Circuits for VLSI", Hartung-Gorre, Konstanz, Germany, Series in Microelectronics, Volume 52, ISBN 3-89649-013-3. 

Journal Papers

  • Robert Rogenmoser, Larry Clark, "Reducing Transistor Variability For Low Power High Performance Chips", IEEE Micro, March 2013.
  • Wei Li, Robert Rogenmoser, et. al. “LVS verification across multiple power domains for a quad-core microprocessor”, ACM Transaction on Design Automation of Electronic Systems, vol. 11, No. 2, April, 2006.
  • Zongjian Chen, Robert Rogenmoser, et. al. “A 2X load/store pipe for a high performance low power 1GHz embedded processor”, IEEE Journal of Solid-State Circuits, vol. 38, No. 11, November 2003.
  • Robert Rogenmoser and Hubert Kaeslin, "The Impact of Transistor Sizing on Power Efficiency in Submicron CMOS Circuits", IEEE Journal of Solid-State Circuits, vol. 32, No. 7, July 1997. 
  • Robert Rogenmoser and Qiuting Huang, "An 800 MHz 1-Micron CMOS Pipelined 8-bit Adder Using True Single-Phase Clocked Logic-Flip-Flops", IEEE Journal of Solid-State Circuits, vol. 31, No.3, March 1996. 
  • Qiuting Huang and Robert Rogenmoser, "Speed Optimization of Edge-Triggered CMOS Circuits for Gigahertz Single-Phase Clocks", IEEE Journal of Solid-State Circuits, vol. 31, No. 3, March 1996. 

Conference Papers

  • Vineet Agrawal, Robert Rogenmoser, et. al. "Low Power ARM® Cortex™-M0 CPU and SRAM Using Deeply Depleted Channel (DDC) Transistors with VDD Scaling and Body Bias", CICC 2013, San Jose, USA, 2013
  • Sang-Soo Lee, Robert Rogenmoser, et. al. "A Slew-Rate Based Process Monitor and Bi-directional Body Bias Circuit for Adaptive Body Biasing in SoC Applications", CICC 2013, San Jose, USA, 2013
  • Robert Rogenmoser, "Integration Challenges and Opportunities", Panel at the Global Semiconductor Alliance (GSA) Silicon Summit 2013, Mountain View, USA, 2013
  • Larry Clark, Robert Rogenmoser, et. al. "A Highly Integrated 65-nm SoC process with Enhanced Power/Performance of Digital and Analog Circuits", IEDM 2012, San Francisco, USA, 2012
  • Robert Rogenmoser, "Reducing Transistor Variability For Low Power High Performance Chips", HotChips 24, Cupertino CA, USA 2012.
  • Robert Rogenmoser, “Low Transistor Variability - Key to Energy Efficient ICs”, Berkley Energy Efficient Electronics Symposium 2011, Berkley, USA, 2011.
  • Zongjian Chen, Robert Rogenmoser, et. al. “A 2X load/store pipe for a high performance low power 1GHz embedded processor”, ISSCC 2003, San Francisco, USA, 2003.
  • Robert Rogenmoser, Lief O'Donnell, and Steve Nishimoto, "A Dual-Issue Floating-Point Coprocessor with SIMD Architecture and Fast 3D Functions", ISSCC 2002, San Francisco, USA, 2002. 
  • Sri Santhanam, Robert Rogenmoser, et.al., "A 1GHz Power Efficient Single Chip Multiprocessor System For Broadband Networking Applications" in Symposium on VLSI Circuits, Kyoto, Japan, 2001. 
  • Robert Rogenmoser, Simon Tam, and Richard McGowen, "Merced Mindelay Methodology", in Proceedings of the 1999 Intel Design, Test, and Technology Conference (DTTC), San Jose, 1999. 
  • Robert Rogenmoser, Hubert Kaeslin, and Norbert Felber, "The Impact of Transistor Sizing on Power Efficiency in Submicron CMOS Circuits", ESSCIRC'96, Neuchatel, Switzerland, 1996. 
  • Robert Rogenmoser, Hubert Kaeslin, and Tobias Blickle, "Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits", Proceedings of PPSN'96, Berlin, Germany, 9/1996. 
  • R. Rogenmoser and Q. Huang, "A 375 MHz 1-Micron CMOS 8-bit Multiplier", in Proceedings of the 1995 Symposium on VLSI Circuits, Kyoto, 1995. 
  • R. Rogenmoser and Q. Huang, "An 800 MHz 1-Micron CMOS Pipelined 8-bit Adder Using True Single-Phase Logic-FFs", in Proceedings of the IEEE CICC'95, Santa Clara, 1995. 
  • R. Rogenmoser, Q. Huang, and F. Piazza, "1.57 GHz Asynchronous and 1.4 GHz Dual-Modulus 1.2 micron CMOS Prescalers", in Proceedings of the IEEE CICC'94, San Diego, 1994. 
  • Q. Huang and R. Rogenmoser, "A Glitch-Free Single-Phase CMOS DFF for Gigahertz Applications", in Proceedings of the IEEE ISCAS'94, London, 1994. 
  • R. Rogenmoser, N. Felber, Q. Huang, and W. Fichtner, "1.16 GHz Dual-Modulus 1.2 micron CMOS Prescaler", in Proceedings of the IEEE CICC'93, San Diego, 1993. 

List of Patents