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Google Glass: New Direction Needed for Chip Designs

New innovative products require new design styles. Google Glass came out a few months ago in April 2013 and has been all over the press. It is a striking design, in which the developers managed to put all electronics into a small box attached to the frame of the glasses. Google Glass Head PictureWhile impressively small, the designers would doubtlessy like to fit everything into the frame instead of having an annoying box on the side. This means that all components need to be long and thin, in particular the integrated circuits (ICs). However, making ICs long and thin so that they can be mounted inside the frame is easier said than done. This blog discusses the challenges and possible approaches to achieve it. 

The biggest ICs in the Google Glass are pictured below (a detailed tear down and sources of all pictures on this page can be found at http://www.catwig.com/google-glass-teardown). From the left there is a flash memory from SanDisk, DRAM from Elpida, and an OMAP application processor (AP) from TI. 

These ICs are close to square form factors of about 8 to 10mm on a side and typically 300µm thick. As an IC customer, Google could just simply request its suppliers to build and deliver these chips in a different form factor, for example, in a 2x50mm sliver instead of 10x10mm square. This would provide the same chip area for the IC designer and would fit inside the frame. While there are ICs that come in such form factors (e.g. LED drivers) and manufacturing is possible, it is not a good option for the application processor, memories, and flash chips.

Building ICs in long slivers adds a lot of internal delay, lowers frequency and performance, and increases power dissipation. Blocks which in a traditional square-like chip were just sitting next to each other have to be lined up serially. Signal connection that were running short before now have to travel long distances impacting frequency and power. Moreover, extra space has to be added to build a communication bus, which increases area and cost. In addition, mounting several of these slivers on a PCB further degrades the systems speed and performance. A different solution has to be found: Rather than lining things up laterally, ICs should be built vertical! 

Going vertical (or up, or 3D) is a more attractive option - basically we take an existing IC, redesign it so that it can be broken into 4 long slivers and stack them on top of each other. For example, a chip that measures 8x8mm is cut into 4 chips each 8x2 mm in area, which are then put on top of each other (see graph below). Grinding these chips to 50µm thickness results in a block that is 8x2mm in area and 200µm thick (4x50µm). The connection between the 4 dies are made using through silicon vias (TSV), a technology that has been demonstrated to work down to 1µm vias. Going vertical adds a little delay between the 4 chip slivers - it is just 50µm up through using a thick TSV wire - but such a design measuring 2x8mm is far more superior to having all these blocks lined up in a 2x32mm area.

3D memoryExisting ICs cannot simply be cut and stacked - any such chip must be engineered and designed to become stackable. Memories and flash chips can easily be implemented that way. These chips consist of many regular, identical and small memory or flash arrays that can be split up and designed to become stackable slivers (see graph above). The AP poses a bigger challenge as it consists of many different sized blocks like CPU cores, caches, GPUs, interface and other SOC blocks. Essentially a new AP has to be architected, designed, and implemented with stacking in mind. For example, the first sliver might contain the GPUs, the next one the CPU cores, followed by the caches, with all the SOC blocks on the fourth sliver. The graph below shows a potential architecture for such a design. A stacked design will not just provide smaller form factors but also higher performance and lower power designs can be achieved due to the shorter signal lengths.

To achieve the goal of hiding all electronics inside the frame of Google Glass, Google will need to procure custom parts for the AP, flash, memory, and any other large IC using stacked IC slivers. Standard blocks will not provide a solution that can be fitted into the glass frame.

New applications - like Google Glass - help drive innovation in IC designt. Chip designers of flash, memory, and application processors have to deal with new interesting challenges and provide new form factors for products like Google Glass and beyond.